SystemC and ANSI-C Based Design and Synthesis Simplifies Design and Delivers Outstanding Quality of Results for the Newest Family of FPGA Devices from Xilinx
Abingdon, Oxfordshire — September 27th, 2004 — Celoxica, the leading provider of C-based design and synthesis solutions, today announced it will support the newly introduced Virtex-4 FPGAs through the latest release of its suite of system design and synthesis tools.
Celoxica¡¯s tools, the DK Design Suite and Agility Compiler synthesize highly complex algorithms described in C or SystemC direct to the FPGA fabric. Alternatively the designer can use the same algorithmic description and output RT level VHDL and Verilog. To make best use of the Virtex 4 architecture synthesis support includes memory tiling, logic packing, automatic use of fast carry logic, packing of arithmetic functions into Xtreme DSPÔ slices and options for retiming.
¡°With our Virtex-4 family scaling to densities of 200,000 logic cells, the industry's highest, Electronic System Level (ESL) design tools play an increasingly important role in helping designers to more quickly investigate, explore and implement large capacity designs,¡± said Steve Lass, Director Software Marketing at Xilinx. ¡°By taking design entry to higher levels of abstraction, Celoxica helps our mutual customers to quickly map large and complex design functions easily and efficiently into our FPGA devices¡±
¡°As modern programmable logic devices such as the Virtex-4 continue to deliver ever more density and functionality, designers must be enabled to quickly exploit all of the features available,¡± said Jeff Jussel, vice president of marketing for Celoxica. ¡±Using the most advanced, high-level synthesis technology our DK Design Suite and Agility Compiler deliver the specification to silicon productivity that today¡¯s designers demand and match excellent QoR results with processor and co-processor support to provide a complete programmable design solution.¡±
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