Agility, ¿µ»ó ¹× ½Åȣ󸮸¦ À§ÇÑ ÇÁ·Î±×·¡¸Óºí Ç÷§Æû ¹ßÇ¥
PALO ALTO, Calif. June 24 2008 - º¹ÀâÇÑ À̹ÌÁö ÇÁ·Î¼¼½Ì ¾Ë°í¸®ÁòÀÇ ½Å¼ÓÇÑ implementationÀ» °¡´ÉÄÉ ÇÏ´Â ¼±µÎ ¼Ö·ç¼Ç Á¦°ø ¾÷ü, Agility Design Solutions »ç´Â ±ÝÀÏ RC240 ÇÁ·Î±×·¡¸Óºí °³¹ß ¹× ÇÁ·ÎÅä ŸÀÔ Ç÷¿ÆûÀ» ¹ßÇ¥Çß½À´Ï´Ù.
( http://www.agilityds.com/literature/rc240_datasheet_01000_screen.pdf )
FPGA¿Í ARM CPU¸¦ ÅëÇÕÇØ ¾Ë°í¸®ÁòÀÇ ÇÁ·ÎÅäŸÀÌÇÎÀ» ¼ö°³¿ù ´ÜÃà ÇÒ ¼ö ÀÖ´Â RC240Àº FPGA¿Í ARM922 TÄھ žÀçÇØ, µðÁöÅÐ ¿£ÅÍÅ×ÀÎ¸ÕÆ®, Åë½Å, ÀÚµ¿Â÷ ÀÎÆ÷Å×ÀÎ¸ÕÆ®(infotainment), ·Îº¿ ±×¸®°í ¸Ó½Å ºñÀü ¾îÇø®ÄÉÀÌ¼Ç µîÀÇ °í¼º´É 󸮸¦ À§ÇÑ ¾Ë°í¸®ÁòÀÇ ¼³°è ¹× ÃÖÀûÈ¿¡ ÀÌ»óÀûÀÎ ½Ã½ºÅÛÀ» °®Ãß°í ÀÖ½À´Ï´Ù.
RC 240Àº ¼³°èÀÚ°¡ ÀÚÁÖ »ç¿ëµÇ´Â ÁÖº¯ÀåÄ¡ ¹× ÀÎÅÍÆäÀ̽º¸¦ Æø³Ð°Ô Áö¿øÇÏ´Â À¯¿¬ÇÑ ÇÁ·ÎÅäŸÀÔ Ç÷§ÆûÀ» Á¦°øÇÔÀ¸·Î½á, °³¹ßÀÚ°¡ Á÷Á¢ ÁÖº¯ÀåÄ¡³ª ÀÎÅÍÆäÀ̽ºÀÇ ¿¬°á¿¡ ´ëÇÑ °³¹ßº¸´Ù µ¶ÀÚÀûÀÎ ¾Ë°í¸®ÁòÀÇ ÀÓÇø®¸àÅ×À̼ǿ¡ ÁýÁßÇÒ ¼ö ÀÖ°Ô µðÀÚÀεǾú½À´Ï´Ù. ÀϹÝÀûÀÎ °æ¿ì ÇÁ·ÎÁ§Æ® ¿Ï¼º¿¡ °É¸®´Â ±â°£À» 75% ´ÜÃà ÇÒ ¼ö ÀÖ½À´Ï´Ù.
¡°RC240Àº ½Å¼ÓÇÑ ¾Ë°í¸®Áò ÀÓÇø®¸àÅ×À̼ÇÀ» À§ÇØ AgilityÀÇ Ç³ºÎÇÑ ÁÖº¯ÀåÄ¡ ¹× ÀÎÅÍÆäÀ̽ºÀÇ ¶óÀÎ ¾÷À» ÇÑÃþ ´õ È®ÀåÇÑ Á¦Ç°ÀÔ´Ï´Ù.¡± AgilityÀÇ C ¼Ö·ç¼Ç ºñÁî´Ï½º ´ã´ç ºÎ»çÀå, Jeff JusselÀº ÀÌ¿Í °°ÀÌ ¸»Çϰí ÀÖ½À´Ï´Ù. ¡°RC240À» ÀÌ¿ëÇØ °í°´Àº ¾Ë°í¸®ÁòÀÇ È¿À²¼º°ú ¼º´ÉÀ» FPGA »óÀÇ Çϵå¿þ¾î¿Í ÀÓº£µðµå ÇÁ·Î¼¼¼ÀÇ ¼ÒÇÁÆ®¿þ¾î ¾çÂÊ ¸ðµÎ ÃÖÀûÈ ÇÒ ¼ö ÀÖ½À´Ï´Ù. AgilityÀÇ °·ÂÇÑ DK Design Suite ¹× ´Ù¾çÇÑ º¸µå API ¶óÀ̺귯¸®¸¦ ¿¬µ¿ÇÔÀ¸·Î½á, FPGA¸¦ óÀ½ ÀÌ¿ëÇÏ´Â À¯Àúµµ RC240Àº FPGA ±â¹ÝÀÇ ÀÓº£µðµå ½Ã½ºÅÛÀÇ ¾Ë°í¸®Áò °³¹ßÀ» ºü¸£°Ô ÇÒ ¼ö ÀÖ½À´Ï´Ù.¡±
RC240Àº 4M °ÔÀÌÆ® Xilinx Virtex-4 LX40 FPGA, 12MbytesÀÇ pipelined SRAM¿¡ Á÷Á¢ ¾ï¼¼½º, FPGA ¿ëµµÀÇ 128Mbytes SDRAM, ARM CPU ¿ëµµÀÇ 128Mbytes¸¦ °¡Áö°í ÀÖ½À´Ï´Ù. RC240Àº À̹ÌÁö¿Í ½Ã±×³Î ó¸® ¾Ë°í¸®ÁòÀ» ½Å¼ÓÇÏ°Ô °³¹ß ¹× ÇÁ·ÎÅäŸÀÔÇÎÇϵµ·Ï ¿Ïº®ÇÑ ¼Ö·ç¼ÇÀ» Á¦°øÇϱâ À§ÇØ AgilityÀÇ PixelStreams ºñµð¿À IP ¶óÀ̺귯¸®¿Í C¸¦ FPGA·ÎÀÇ ¼³°è ȯ°æÀÎ DK Design Suites µÑ´Ù¿¡ ÀÇÇØ Áö¿øµË´Ï´Ù.
The RC240 peripherals and interfaces include:
Video
• Camera-link interface
• Optional CMOS Camera
• VGA/DVI output
• Optional 8.1¡± 1024 x 768 LCD Touchscreen
Audio AC97 compatible
• On-board microphone and stereo speakers
• Line-level input (stereo)
• Line/headphones output (stereo)
Communications
• USB 2.0: 1x to FPGA, 1x to ARM, 2x from ARM
• Gigabit Ethernet
• RS232
Extras
• 3 axis acceleromet
• Dual channel 65Msps A to D converter inputs
• Dual channel 125Msps D to A converter outputs
• CAN bus
• 4 servo control outputs
• ATA compatible expansion port
• SDIO card socket
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